The present invention relates to an automatic gain control (ACG) circuit, and more particularly to an AGC circuit with high linearity and monotonically correlated offset voltage.
Automatic Gain Control (AGC) circuits are used in many communication and signal processing applications. For example, in the receiver of a wired or wireless communication link, the intended signal to be processed may be a short distance away and therefore relatively strong while another signal may be a long distance away and much weaker. The receiver must process both the strong signals and the weak signals which implies a variable gain function. High gain is used to detect and amplify weak signals and low gain and/or attenuation is used to process strong signals.
In certain architectures, such as a zero intermediate frequency (ZIF) radio architecture and the like, the AGC function requires a relatively large maximum voltage gain and wide total gain range capability. Further, the gain range must be relatively matched across two baseband channels (I and Q). In order to facilitate a fast response control loop which sets the AGC, it is desired that the AGC have very good absolute gain control across process variations and temperature. The AGC should have excellent low noise and linearity performance, and work with a limited voltage supply. Additional requirements may be necessary, such as relatively high symmetry and well controlled overdrive characteristics and low overall power dissipation.
Ideal amplifiers have no input offset voltage but the inevitable mismatch between components during manufacturing results in a finite value. Input offset voltage is the apparent DC input voltage when zero input voltage is applied. That is, with zero applied input voltage, the output voltage is nonzero. The input offset voltage is equal to this output voltage divided by the amplifier voltage gain. In a ZIF radio architecture, the input offset voltage needs to be corrected before low level signals can be detected or accurately decoded. The offset correction must occur very quickly, but is complicated by the fact that the input offset voltage changes as the amplifier gain is changed. So if the input offset voltage can not be eliminated altogether, then the next best case is to have its dependency upon gain be predictable so the correction process can be as quick as possible.
The most simple gain stage that can implement an AGC function is the basic differential pair of transistors. An exemplary differential pair stage includes a pair of bipolar transistors Q1, Q2 having their emitters coupled together and to a bias current sink. A pair of load or bias resistors is each coupled between a respective collector of the differential pair and a voltage supply signal. A differential input is applied across the bases of the transistors, and a differential output is developed across the respective collectors. The gain of this stage is the transconductance of either transistor Q1 or Q2 multiplied by the load resistance. By simply varying the transconductance, the gain is changed. The transconductance can be varied by changing the bias current. A fundamental problem with this type of AGC circuit is that it has limited input signal swing capability. Input differential voltages of approximately 50 millivolts (mV) peak to peak begin to cause significant nonlinearities, which are unacceptable in many applications. Such nonlinearities, for example, may result in a total harmonic distortion (THD) that is greater than 1%. In high performance systems, AGC functions may need to handle input differential voltages as large as two (2) volts (V) peak to peak, making this AGC stage unacceptable.
The next most common gain stage used for AGC functions is the differential pair with emitter degeneration. The gain stage with emitter degeneration is similar to the simple gain stage just described and further includes a pair of emitter degeneration resistors to increase the input signal swing capability. In particular, the emitters of the differential pair of transistors Q1, Q2 are not connected to each other. Instead, each emitter is coupled to one end of a respective one of the emitter degeneration resistors. The other ends of the resistors are coupled together and to the bias current sink. The emitter degeneration resistors are ideally linear. The overall transconductance of this stage is decreased by the emitter resistors and their presence allows for more of the input signal to appear across these resistors than across the nonlinear base-emitter junctions of the transistors Q1 or Q2. This results in significantly improved linear handling of large input differential voltages. As the emitter resistors are increased, however, the overall transconductance of the stage becomes less and less dependent on the transistor""s transconductance and more dependent on the emitter resistors. A fundamental problem with this arrangement is that the ability to vary the gain by changing the bias current is severely limited as the emitter resistors are increased.
More advanced AGC circuits have been suggested. One idea is to provide an analog attenuator in front of a fixed gain operational amplifier (op-amp). There are several problems with this arrangement for certain applications. First, the analog attenuator circuit requires a stack (cascode) of at least three transistors and resistors, which reduce voltage swing capability. Next, placing an attenuator in front of a large fixed gain amplifier forces the resistors that make up part of the attenuator circuitry to be very low-valued in order to meet reasonable noise performance. These low valued resistors require significant supply current.
None of the solutions described above meet all of the desired characteristics of an AGC circuit for use in a ZIF architecture.
An automatic gain control (AGC) circuit according to an embodiment of the present invention includes a high gain amplifier, a feedback network and first and second transconductance amplifiers. The high gain amplifier has an output that asserts an output signal of the AGC circuit. The feedback network has a first end that receives an input signal of the AGC circuit, a second end coupled to the output of the high gain amplifier and first and second intermediate nodes. Each transconductance amplifier has an input coupled to a respective one of the first and second intermediate nodes of the feedback network and an output coupled to the input of the high gain amplifier. The transconductance amplifiers collectively control a position of a virtual ground within the feedback network to control gain of the AGC circuit. The transconductance amplifiers each include an attenuator coupled to the feedback network, and a transconductance stage coupled to the attenuator and to the input of the high gain amplifier.
Each transconductance amplifier is configured to operate linearly across a relatively wide input voltage range. The AGC circuit is preferably configured so that its input offset voltage varies monotonically with gain of the AGC circuit. Although it may be desired not to have any input offset voltage, a predictable offset voltage is easily compensated and reduced or eliminated.
In one embodiment, the high gain amplifier is a differential amplifier that has a differential input and a differential output with first and second polarity outputs. The feedback network includes first and second intermediate differential nodes. Each transconductance amplifier has a differential input coupled to a respective one of the first and second intermediate differential nodes of the feedback network and a differential output coupled to the differential input of the differential amplifier. The feedback network may be implemented in any of several manners. In an illustrated configuration, the feedback network includes first and second sets of resistors, where each resistor set is coupled in series between a respective polarity of the input signal and a corresponding output polarity of the differential amplifier and forms corresponding intermediate nodes. The intermediate nodes of the series-coupled resistor sets collectively form the intermediate differential nodes.
In the differential configuration, the attenuator of each transconductance amplifier is coupled to a corresponding intermediate differential node of the feedback network. Also, each transconductance stage has an input coupled to a corresponding attenuator and a differential output coupled to the differential input of the differential amplifier. In a more specific configuration, the attenuator includes first and second differential to single ended transconductance stages and a resistive device coupled between the pair of transconductance stages. Each differential to single ended transconductance stages may include a current mirror, a differential pair of transistors coupled to the current mirror, and a bias current device coupled to the differential pair of transistors. The bias current device of each transconductance stage sinks a current that is proportional to absolute temperature.
The attenuator outputs first and second intermediate differential signals, where a first polarity of the first intermediate differential signal is a first polarity of a corresponding intermediate node pair and where a first polarity of the second intermediate differential signal is a second polarity of the corresponding intermediate node pair. Each transconductance stage of the transconductance amplifiers includes first and second pairs of differential transistors and at least one bias current device. The first pair of differential transistors receive the first intermediate differential signal and provides a first polarity of a differential output signal. The second pair of differential transistors receives the second intermediate differential signal and provides a second polarity of the differential output signal. The one or more bias current devices bias the first and second pairs of differential transistors. In a specific embodiment illustrated, the attenuator and transconductance stage of each transconductance amplifier are each implemented using bipolar junction transistors. It is understood, however, that different types of transistors and/or circuit components may be employed to achieve similar functionality, so that the present invention is not limited to any particular circuit implementation.
In one embodiment, a first bias current device is coupled to bias the transconductance stage of the first transconductance amplifier and a second bias current device is coupled to bias the transconductance stage of the second transconductance amplifier. Further, the first and second bias current devices may be controllable current sources that are controlled to modify gain of the AGC circuit. For enhanced linearity, a current sum of the controllable current sources remains constant across a gain range. The controllable current sources may be controlled by a single differential current signal, and may be electronically controllable. The bias current control devices may be variable between a predetermined maximum current level and a predetermined minimum current level to control gain. Thus, one bias current control device is linearly increased while the other is linearly decreased so that the total bias current remains substantially constant.
It is appreciated that a gain circuit as described herein has a gain that is varied as the virtual ground is varied. The gain is determined by a resistor and/or transconductance ratio, which can change linearly, exponentially (e.g., linear in dB), or according to any other useful function. The maximum undistorted signal level may be scaled by resistors and does not require more than two input stages. Linearity may be adjusted independently of the feedback resistive network. A gain control network is provided which is within and part of the closed loop amplifier gain circuit. The gain circuit may be DC or AC coupled, and may be cascaded with other similar gain circuits. A differential gain circuit is disclosed that does not require a common mode reference. The gain circuit has a low absolute gain tolerance and excellent gain matching across different gain circuits on the same silicon die of an IC. A control circuit is described that allows optimization of both noise and linearity performance in the gain circuit. This capability is allowed for by individually sequencing transconductance cells that make up the gain circuit so that only two are active at any given time. The control circuit may implement a ramp function which has precise current ratio capability and precise turn-on and turn-off set points. The control circuit may also be cascaded if desired. Although the input offset error voltage is not eliminated, it nonetheless changes monotonically with gain making offset voltage correction predictable for easy compensation.